Embedded memory designs are constantly trying to improve performance (reducing memory cycle time or memory access time and/or increasing bandwidth) in order to enable new capabilities for systems on a chip. Many different architectural tradeoffs are made in the pursuit of such improved performance. For example, one tradeoff to enable improved access/cycle time of a memory is to require control/data inputs to the memory to be setup to the memory clock by increasingly larger percentages of the clock cycle time. A different tradeoff to enable improved bandwidth of a memory is to increase the width of the memory data bus. As the width of the data bus increases, though, the clock skew between physically distant data bits can increase. This can lead to larger data setup/hold requirements relative to the clock cycle time.
Another issue that is causing setup/hold times to become a larger requirement relative to a memory's overall cycle/access time is that most input paths relative to the clock travel through relatively standard combinatorial digital gate delays. This can be contrasted with the actual internal data path, which is often of a more complex/analog nature (using sense-amplified signals, domino logic, etc.). Changing the architecture of the internal data path can result in a very large reduction in the memory cycle/access time, whereas little can often be done to change the input signal setup and hold times. The net of all of these issues is that setup/hold requirements for memory inputs is often becoming a larger percentage of the overall cycle time, making these requirements more difficult to satisfy.
At the same time, as technology features decrease, memory designs are becoming much more susceptible to various defect mechanisms that can only be discovered by testing under very specific conditions. Test logic, often BIST (built in self test) and/or BISR (built in self repair) circuitry, must be capable of working correctly under a wide variety of conditions, often far outside the normal customer application ranges for temperature and voltage. This leads to a need for an extremely robust memory interface that allows test circuitry to correctly access the memory under diverse conditions, while at the same time allowing for high performance customer applications with setup/hold times adequately met.
Solutions to the above problems have not adequately addressed both the hold time and setup time issues. For example, FIG. 1a shows a structure, which has a large hold margin and a small setup margin, with RAM_DATA being launched off of the rising edge triggered Flip-Flop when CLK falls. A timing diagram showing the large hold margin and small setup margin of the structure of FIG. 1a is shown in FIG. 1b. 
More specifically, as shown in FIGS. 1a and 1b, to provide an interface all data is basically launched to the memory off of the opposite edge of the clock. Note that if the RAM setup/hold requirements are related to the rising edge of the clock, the data would be launched to the RAM off of a negative edge triggered latch. This ensures all hold times are met by providing a half cycle of hold margin as shown in FIG. 1b. If there is a hold issue at a particular frequency the clock cycle can simply be slowed down until there is enough hold margin to access the memory, allowing for correct test capability under diverse conditions, albeit at a lowered frequency. However, this same technique of launching data to the array off of the opposite clock edges also means there is only a half cycle for setup (see FIG. 1b). Memory setup requirements can always be made to pass if the cycle time is decreased, but this can lead to severe performance issues. The setup requirements for the memory can often dictate the overall allowable cycle time.
In comparison, the structure of FIG. 2a provides a large setup margin and a small hold margin. This is shown more specifically in the timing diagram of FIG. 2b. In particular, referring to FIGS. 2a and 2b, in an interface where the data is launched to the memory on the same edge the memory setup/hold requirements are related, hold issues can easily develop under many conditions (particularly under high voltage test corners). A full cycle is available for setup, but nothing can be done to mitigate hold time issues, which can cause severe test failures at even relatively benign test conditions.
Those skilled in logic design will recognize that where positive/negative edge triggered flip-flops have been described above, level sensitive scan design (LSSD) latches could be used (positive edge triggered operation approximated by using the LSSD L2 output and negative edge triggered operation approximated using the LSSD L1 output). Regardless of the exact latching circuitry/clocking methodology chosen, though, the same issues are still encountered.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.